cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 1/6 BTD1816I3 cystek product specification low vcesat npn epitaxial planar transistor bv ceo 100v i c 4a r cesat BTD1816I3 50m features ? low collector-to-emitter saturation voltage ? high-speed switching ? large current capability ? good linearity of h fe ? high f t ? rohs compliant package applications ? suitable for relay drivers, high speed inverters, conve rters, and other high curre nt switching applications. symbol outline BTD1816I3 b base c collector e emitter to-251 b c b c e
cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 2/6 BTD1816I3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit collector-base voltage v cbo 120 v collector-emitter voltage v ceo 100 v emitter-base voltage v ebo 6 v collector current (dc) i c 4 collector current (pulse) i cp 8 (note 1) a base current i b 1.2 a power dissipation @ t a =25 c p d 1 power dissipation @ t c =25 c p d 20 w thermal resistance, junction to ambient r ja 125 c/w thermal resistance, junction to case r jc 6.25 c/w junction temperature tj 150 c storage temperature tstg -55~+150 c note : 1. single pulse , pw 380 s, duty 2%. characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv cbo 120 - - v i c =10 a, i e =0 *bv ceo 100 - - v i c =1ma, i b =0 bv ebo 6 - - v i c =10 a, i c =0 i cbo - - 1 a v cb =100v, i e =0 i ebo - - 1 a v eb =4v, i c =0 *v ce(sat) 1 - 50 120 mv i c =1a, i b =50ma *v ce(sat) 2 - 90 250 mv i c =2a, i b =200ma *v be(sat) - 0.9 1.2 v i c =2a, i b =200ma *h fe 1 180 - 560 - v ce =5v, i c =500ma *h fe 2 120 - - - v ce =5v, i c =3a f t - 180 - mhz v ce =10v, i c =500ma cob - 40 - pf v cb =10v, f=1mhz t on - 100 - ns t stg - 900 - ns t f - 50 - ns v cc =50v, i c =10i b 1=-10i b 2=2a, r l =25 *pulse test : pulse width 380 s, duty cycle 2% classification of h fe 1 rank r s range 180~390 270~560 ordering information device package shipping marking BTD1816I3 to-251 (rohs compliant) 80 pcs / tube, 50 tubes / box d1816
cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 3/6 BTD1816I3 cystek product specification characteristic curves current gain vs collector current 10 100 1000 1 10 100 1000 10000 collector current---ic(ma) current gain---hfe vce=5v vce=1v vce=2v saturation voltage vs collector current 10 100 1000 10000 1 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) vce(sat) ic=20ib ic=50ib ic=100ib saturation voltage vs collector current 100 1000 10000 1 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) vbe(sat) @ ic=10ib on vottage vs collector current 100 1000 1 10 100 1000 10000 collector current---ic(ma) on voltage---(mv) vbe(on)@vce=5v grounded emitter output characteristics 0 0.5 1 1.5 2 2.5 3 3.5 0246810 collector-to-emitter voltage---vce(v) collector current---ic(a) ib=0ma ib=1ma ib=5ma ib = 8m a grounded emitter output characteristics 0 1 2 3 4 5 6 7 8 012345 collector-to-emitter voltage---vce(v) collector current---ic(a) ib=0ma ib=2ma ib=5ma ib = 7m a ib=10ma ib=20m a ib=30ma ib=50m a ib=100ma ib=70ma ib=60ma ib=80ma ib = 90 m a ib = 40 m a
cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 4/6 BTD1816I3 cystek product specification characteristic curves(cont.) power derating curve 0 0.2 0.4 0.6 0.8 1 1.2 0 50 100 150 200 ambient temperature---ta() power dissipation---pd(w) power derating curve 0 5 10 15 20 25 0 50 100 150 200 case temperature---tc() power dissipation---pd(w)
cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 5/6 BTD1816I3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c ? time(ts min to ts max ) 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c821i3 issued date : 2005.10.05 revised date :2009.02.04 page no. : 6/6 BTD1816I3 cystek product specification to-251 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0177 0.0217 0.45 0.55 g 0.2559 - 6.50 - b 0.0354 0.0591 0.90 1.50 h - *0.1811 - *4.60 c 0.0177 0.0236 0.45 0.60 i - 0.0449 - 1.14 d 0.0866 0.0945 2.20 2.40 j - 0.0346 - 0.88 e 0.2441 0.2677 6.20 6.80 k a e f g h j i 3 2 1 k c d b marking: d1816 style: pin 1.base 2.collector 3.emitter 3-lead to-251 plastic package cystek packa g e code: i3 0.2047 0.2165 5.20 5.50 f 0.2677 0.2835 6.80 7.20 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: kfc; pure tin plated ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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